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4m pixel cmos image senso r lupa-4000 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05712 rev. *b revised januari 4, 2007 preamble overview this document describes the inte rfacing and the driving of the lupa-4000 image sensor. this 4 mega-pixel cmos active pixel sensor features synchronous shutter and a maximal frame-rate of 15 fps in full resolution. the readout speed can be boosted by means of sub sampling and windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double and multiple slope functionality. the sensor can be used with one or two outputs. two on chip 10-bit adc's can be used to convert the analog data to a 10-bit digital word stream. the sensor uses a 3-wire serial-parallel (spi) interface. it is housed in a 127-pin ceramic pga package. this data sheet allows the us er to develop a camera-system based on the described timing and interfacing. main features the main features of the image sensor are identified as: ? 2048 x 2048 active pixels (4m pixel resolution) ?12 m 2 square pixels (based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)) ? peak qe x ff of 37.50% ? optical format: 24,6 mm x 24,6 mm ? pixel rate of 66 mhz using a 33 mhz system clock ? optical dynamic range: 66 db (2000:1) in single slope operation and up to 90 db in multiple slope operation ? 2 on-chip 10 bit, 33 msamples/s adc ? full snapshot shutter ? random programmable windowing and sub-sampling modes ? 127-pin pga package ? binning (voltage averaging in x-direction) ? programmable read out direction (x and y) part number and ordering information the lupa-4000 is also available in color or monochrome without the cover glass. please contact cypress for more information. name package mono- chrome/color CYIL1SM4000AA-GDC 127 pin ceramic pga monochrome [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 2 of 38 table of contents preamble ...................................................................................................................... ..................................... 1 overview ...................................................................................................................... ................................ 1 main features ................................................................................................................. .............................. 1 part number and ordering information........................................................................................... ............... 1 specifications ........ ........................................................................................................ ................................... 4 general specifications ........................................................................................................ .......................... 4 electro-optical specifications ................................................................................................ ........................ 4 features and general specifications ........................................................................................... ................. 6 electrical specifications ..................................................................................................... ........................... 7 sensor architecture ........................................................................................................... ............................... 8 the 6-t pixel ................................................................................................................. ............................... 8 frame rate and windowing ......... ............................................................................................. ..................... 9 output amplifier .............................................................................................................. .............................. 9 pixel array drivers ........................................................................................................... ............................. 10 column amplifiers ................ ............................................................................................. ........................... 10 analog to digital converter ......................... .......................................................................... ....................... 10 synchronous shutter ........................................................................................................... ......................... 11 non-destructive readout (ndr) ................................................................................................. .................. 12 operation and signalling ...................................................................................................... ........................ 12 pixel array signals ........................................................................................................... ............................. 14 timing and read out of the image sensor ....................................................................................... ............... 16 timing of the pixel array ..................................................................................................... .......................... 16 read out of the image sensor ........................ .......................................................................... .................... 18 serial-parallel-interface (spi) ..................... .......................................................................... ....................... 24 pin list ...................................................................................................................... .......................................... 25 geometry and mechanical specifi cations ........................................................................................ .............. 29 bare die ...................................................................................................................... .................................. 29 package drawing ............................................................................................................... .......................... 30 bonding pads .................................................................................................................. ............................. 32 bonding diagram ............................................................................................................... ........................... 33 glass transmittance ....................................... .................................................................... .......................... 34 handling and soldering precautions ............................................................................................ .................. 35 ordering information .. ........................................................................................................ .......................... 35 disclaimer .................................................................................................................... ................................ 35 appendix a: lupa-4000 evaluation system ........... ................. ................ ................ ................ ........... ......... 36 appendix b: frequently asked qu estions ........... ................ ................. ................ ................ ............ ........... 37 document history page ......................................................................................................... .......................... 38 list of figures spectral response curve ....................................................................................................... .............................. 5 photo-voltaic response curve .................................................................................................. ........................... 6 block diagram of the image sensor ............................................................................................. ....................... 8 6t-pixel architecture ......................................................................................................... .................................. 8 output stage architectu re ..................................................................................................... .............................. 9 adc timing .................................................................................................................... ..................................... 10 in- and external adc connections .............................................................................................. ........................ 11 [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 3 of 38 synchronous shutter operation ................................................................................................. .......................... 11 principle of non-destructive readout. ......................................................................................... ......................... 12 internal timing of the pixe l.................................................................................................. ................................. 14 integration and read out in para llel .......................................................................................... ........................... 16 integration and readout sequentially .......................................................................................... ........................ 16 timing of the pixel array ...................................................................................................... ................................ 17 readout of the image sensor. f. o.t ............................................................................................. ...................... 18 x- and y-addressing ........................................................................................................... ................................ 19 x-addressing. from botto m to top ............................................................................................... ........................ 20 output signal related to clock_x signal .......... .............................................................................. ....................... 21 standard timing for the r.o.t. only pre_col and norowsel control signals are required .................................... 22 reduced standard rot by means of sh_col signal. ................................................................................ ........... 22 x- and y-addressing with precharg ing of the buses ............................................................................. .............. 23 spi block diagram and timing ........................ .......................................................................... ........................... 24 die figure of the lupa-4000 ................................................................................................... ............................ 29 package drawing of the lupa-4000 package ...................................................................................... .............. 30 lupa-4000 package specifications with die ..................................................................................... .................. 31 placing of the bonding pads on the lupa-4000 package .......................................................................... ........ 32 bonding pads diagram of the lupa-4000 package ................................................................................. .......... 33 transmission characteristics of the d 263 glass used as protective cover fo r the lupa-4000 sensors. ............ 34 content of the lupa-4000 evaluation kit ....................................................................................... .................... 36 dual slope diagram ............................................................................................................ ................................. 37 list of tables general specifications ........................................................................................................ ................................ 4 electro-optical specifications ................................................................................................ .............................. 4 features and general specifications ........................................................................................... ........................ 6 recommended operation conditions .................... .......................................................................... .................... 7 frame rate as function of roi re ad out and/or sub sampling .................................................................... ......... 9 adc specifications ............................................................................................................ ................................. 10 advantages and disadvantages of non-destructive readout. ...................................................................... ........ 12 power supplies ................................................................................................................ ................................... 12 overview of the power supplies related to the pixel signals ................................................................... ............ 13 overview of bias signals ...................................................................................................... ............................... 13 overview of the in- and external pixel array signals ............. ............................................................. ................. 15 timing specifications ......................................................................................................... ................................. 17 read-out timing specifications ................................................................................................ ............................ 19 read-out timing specifications wit h precharching of the buses ............ ..................................................... ......... 23 spi parameters ................................................................................................................ ................................... 24 [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 4 of 38 specifications general specifications electro-optical specifications overview table 1. general specifications parameter specification remarks pixel architecture 6t-pixel based on the high fill-factor active pixel sensor te chnology of fillfactory pixel size 12 m x 12 m the resolution and pixel size results in a 24,6 mm x 24,6 mm optical active area. resolution 2048 x 2048 pixel rate 66 mhz using a 33 mhz system clock and 1 or 2 parallel outputs. shutter type pipelined snapshot shutter full snapshot shutter (integration during read out is possible). full frame rate 15 frames/second frame rate increase possible with roi read out and/or sub sampling. table 2. electro-optical specifications parameter specification remarks fpn <1.25% rms of max. output swing prnu <2.5% rms at 25% and 75% (% of the signal) conversion gain 13.5 uv/electron @ output (measured). output signal amplitude 1v converted by 2 on -chip 10-bit adc's in 2x10 parallel digital outputs. or to be used with external adc's saturation charge 80.000 e- sensitivity 2090 v.m2/w.s average white light. 11.61 v/lux.s visible band only (180 lx = 1 w/m2). peak qe * ff peak sr * ff 37.5% 0.19 a/w average qe*ff = 35%. average sr*ff = 0.15 a/w. see spectral response curve. dark current (@ 21 c) <140 mv/s or 10000 e-/s noise electrons < 40 e- s/n ratio 2000:1 66 db. spectral sensitivity range 400 - 1000 nm parasitic sensitivity < 1/5000 i.e. sensitivit y of the storage node during read out (after integration). mtf 64% power dissipation <200 mwatt typical (without adc's). [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 5 of 38 spectral response curve figure 1. spectral response curve figure 1 shows the spectral res ponse characteristic. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. the sensor is light sensitive bet ween 400 and 1000 nm. the peak qe * ff is 37.5% approximately between 500 and 700 nm. in view of a fill factor of 60%, t he qe is thus larger than 60% between 500 and 700 nm. 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 400 500 600 700 800 900 1000 wavelength [nm] spectral response [a/w] qe 10% qe 20% qe 25% qe 30% qe 40% [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 6 of 38 photo-voltaic response curve figure 2. photo-voltaic response curve figure 2 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron curve is independent of any parameters. the voltage to electrons conversion gain is 13.5 v/electron. note that the upper part of the curve (near saturation) is actually a logarithmic response. features and general specifications 0 0.2 0.4 0.6 0.8 1 1.2 0 20000 40000 60000 80000 100000 120000 140000 #electrons output swing [v] table 3. features and general specifications feature specification/description electronic shutter type full snapshot shutter (integration during read out is possible). windowing (roi) randomly programmable roi read out. sub-sampling and binning modes 2:1 subsampling and volt age averaging is possible (only in the x-direction). read out direction read out direction can be reversed in x and y. extended dynamic range multiple slope (up to 90 db optical dynamic range). analog output the output rate of 66 mpixels/s can be achieved with either 1 or 2 analog outputs. digital output 2 on-chip 10-bit adc's @ 33 msamples/s. supply voltage vdd nominal 2.5v (some supplies require 3.3v). logic levels 3.3v. operational temperature range 0c to 60c; with degradation of dark current. interface serial-to pa rallel interface (spi). package 127 pin pga package power dissipation <200 mw mass <100g [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 7 of 38 electrical specifications absolute maximum ratings vdd dc supply voltage -0.5 to 4.5 v v in dc input voltage -0.5 to 3.8 v v out dc output voltage -0.5 to 3.8 v i io dc current drain per pin; any single input or output. 50 ma t l lead temperature (5 seconds soldering). 350 c ? absolute ratings are those values beyond which damage to the device may occur. ? vdd = vddd = vdda (vddd is supply to digital circuit, vdda to analog circuit). recommended operating conditions output amplifiers differential external output load r > 10 k ? c < 20 pf (<10 pf is advised) number of outputs 1 at 66 mpixels/sec 2 at 33 mpixels/sec table 3. features and general specifications (continued) feature specification/description table 4. recommended operation conditions symbol parameter min. typ. max. unit vaa power supply column read out module 2.5 v va3 power supply column read out module 3.3 3.3 v vdd power supply digital modules 2.5 v voo power supply output stages 2.5 v vres power supply reset drivers 2.5 3.5 3.8 v vres_ds power supply multiple slope reset driver 2.0 2.5 3.3 v vmem_h power supply memory element (high level) 2.5 3.3 3.5 v vmem_l power supply memory element (low level) 2.0 2.6 3.0 v vpix power supply pixel array 2.0 2.6 3.3 v vpre_l power supply for precharge off-state ?0.4 0 0 v t a commercial operating temperature. 0 30 60 c notes 1. all parameters are characterized for dc condit ions after thermal equilibrium has been established. 2. unused inputs must always be tied to an appropriate logic level, e.g. either vdd or gnd. 3. this device contains circuitry to prot ect the inputs against damage due to high stat ic voltages or electric fields; however i t is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 8 of 38 sensor architecture a schematic drawing of the archit ecture is given in the block diagram below. the image core consists of a pixel array, one x- and two y-addressing registers (only one drawn), pixel array drivers and column amplifiers. the image sensor of 2048 * 2048 pixels is read out in progressive scan. one or two output amplifiers read out the image se nsor. the output amplifiers are working at 66 mhz pixel rate no minal speed or each at 33 mhz pixel rate in case the 2 output amplifiers are used to read out the imager. the complete image sensor has been designed for operation up to 66 mhz. the structure allows having a programmable addressing in the x-direction in steps of 2 and in the y-direction in steps of 2 (only even start addresses in x- and y-direction are possible). the starting point of the address is uploadable by means of the serial-parallel interface (spi) figure 3. block diagram of the image sensor the 6-t pixel to obtain the global shutter feature combined with a high sensitivity and good parasitic light sensitivity (pls), the pixel architecture given in the figure below is implemented. figure 4. 6t-pixel architecture column ampli?ers on chip drivers y shift register select drivers eos_y clk_y s ync_y 2 differential outputs eos_x reset, mem_hl, precharge, sample pixel array 2048 * 2048 xshiftregister sync_x clk_x logic blocks dac spi rese t vpix vmem row-selec t sampl e [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 9 of 38 this pixel architecture is designed in a 12 * 12 m 2 pixel pitch. the pixel is designed to meet the specifications as described in table 1 , ta ble 2 , and table 3 . frame rate and windowing frame rate to obtain a frame rate a 15 frames/sec, one needs 1 output amplifier, working at 66 mh z pixel rate or 2 output amplifiers worki ng at 33 mhz each (assuming a row overhead time (rot) of 200 nsec). the frame period of the lupa-4000 sens or can be calculated as follows: frame period = fot + (nr. lines * (rot + pixel period * nr. pixels) with: fot: frame overhead time = 5 s. nr. lines: number of lines read out each frame (y). nr. pixels: number of pixels read out each line (x). rot: row overhead time = 200 ns (nominal; can be further reduced). pixel period: 1/66 mhz = 15.15 ns. example read out of the full resolution at nominal speed (66 mhz pixel rate): frame period = 5 us + (2048 * (200 ns + 15.15 ns * 2048) = 64 ms => 15 fps. roi read out (windowing) windowing can easily be achieved by a serial-parallel uploadable interface in which the starting point of the x- and y-address is uploaded. this downloaded starting point initiates the shift register in the x- and y- direction triggered by the sync_x and sync_y pulse. the minimum step size for the x-address and the y-address is 2 (only even start addresses can be chosen). the size of both address registers is 10 bits. when for instance the addresses 0000000001 and 0000000001 are uploaded, the readout will start at line 2 and column 2. output amplifier 1 output amplifier working at 66 mpixels/sec is required to bring the whole pixel array of 2048 by 2048 pixels at the required frame rate to the outside world. a second output stage is also foreseen to convert the analog data on-chip by 2 10-bit adc's each working at 33 mhz. by having a second output stage working in parallel, the pixel rate can be more relaxed to 33 mhz for both output amplifiers. using only one output-stage, the output signal will be the result of multiplexing between the 2 internal buses. when using 2 output-stages, both outputs will be in phase. each output-stage has 2 outputs . one output is the pixel signal; the second output is a dc signal which offset can be programmed using a 7-bit word. the dc signal can be used for common mode rejection between the 2 signals. the disadvantage is an increase in power dissipation however this can be reduced by setting the highest dac voltage by means of the spi figure 5. output stage architecture. table 5. frame rate as function of roi read out and/or sub sampling image resolution (x*y) frame rate [frames/s] frame readout time [ms] comment 2048 x 2048 15 67 full resolution. 1024 x 2048 31 32 subsample in x-direction. 1024 x 1024 62 16 roi read out. 640 x 480 210 4.7 roi read out. out1: pixel signal out2: dc signal image sensor dac spi 7bits [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 10 of 38 the output voltage of out1 will be between 1.3v (dark level) and 0.3v (white level) and depends on process variations and voltage supply settings. the output voltage of out2 is determined by the dac. pixel array drivers we have foreseen on this image sensor on chip drivers for the pixel array signals. not only the driving on system level is easy and flexible, also the maximum currents applied to the sensor are controlled on chip. this m eans that the charging on sensor level is fixed and that the s ensor cannot be overdriven from externally. in the paragraph on the timing, the operation of the on-chip drivers is explained more in detail. column amplifiers the column amplifiers are designed for minimum power dissi- pation and minimum loss of signal for this reason multiple biasing signals are needed. the column amplifiers also have the "voltage-averaging" feature integrated. in case of voltage averaging mode, the voltage average between 2 columns is taken and read out. in this mode only 2:1 pixels have to be read out. to achieve the voltage-averaging mode, an additional external digital signal called "voltage-averaging" is required in combination with a bit from the spi. analog to digi tal converter the lupa4000 has a two 10 bit flash analog digital converters running nominally at 33 msamples/s. the adc's are electrically separated from the image sensor. the inputs of the adc should be tied externally to the outputs of the output amplifiers. one adc will sample the even columns and the other one will sample the odd columns. although the input range of the adc is between 1v and 2v and the output range of the analog signal is only between 0.3v and 1.3v, the analog output and digital input may be tied to each other directly. this is possible because there is an on chip level-shifter located in front of the adc to lift up the analog signal to the adc range. adc timing the adc converts the pixel data on the falling edge of the adc_clock but it takes 2 clock cycles before this pixel data is at the output of the adc. this pipeline delay is shown in figure . figure 6. adc timing table 6. adc specifications parameter specification input range 1 - 2v (*) quantization 10 bits nominal data rate 33 msamples/s dnl (linear conversion mode) typ. < 0.4 lsb rms inl (linear conversion mode) typ. < 3.5 lsb input capacitance < 2 pf power dissipation @ 33 mhz 50 mw conversion law linear/gamma-corrected note 4. the internal adc range will be typ. 50 mv lower then the external applied adc_vhigh and adc_vlow voltages due to voltage drop s over parasitic internal resistors in the adc. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 11 of 38 setting of the adc reference voltages figure 7. in- and external adc connections the internal resistor r adc has a value of approximately 300 ? . this results in the values for the external resistors: the values of the resistors depend on the value of r adc . the voltage difference between adc_vlow and adc_vhigh should be at least 1.0v to assure proper working of the adc. synchronous shutter in a synchronous (snapshot) shutter light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 8. synchronous shutter operation rhigh_adc 2.5v ref_low ~ 1 v ref_high ~ 2 v rlow_adc r adc externa l interna l externa l resistor value ( ? ) r adc_vhigh 75 r adc 300 r adc_vlow 220 resistor value ( ? ) time axis line number integration time burst readout time common reset common sample&hold flash could occur here [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 12 of 38 figure 8 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and read out cycle can occur in parallel or in sequential mode. (ref. 4. ti ming and read out of the image sensor) non-destructive readout (ndr) the sensor can also be read out in a non-destructive way. after a pixel is initially reset, it can be read multiple times, without resetting. the initial reset level and all intermediate signals can be recorded. high light levels will saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, one has to use the later or latest samples. figure 9. principle of non-destructive readout essentially an active pixel array is read multiple times, and reset only once. the external system intelligence takes care of the interpretation of the data. table 7 summarizes the advantages and disadvantages of non-destructive readout. operation and signalling one can distinguish the different signals into different groups: ? power supplies and grounds ? biasing and analog signals ? pixel array signals ? digital signals ? test signals power supplies and ground every module on chip, as there are: column amplifiers, output stages, digital modules, drivers has its own power supply and ground. off chip the grounds can be combined, but not all power supplies may be combined. this results in several different power supplies, but this is required to reduce electrical cross-talk and to improve shielding, dynamic range and output swing. on chip we have the ground lines of every module which are kept separately to improve shielding and electrical cross talk between them. an overview of the supplies is given in table 8 and table 9 . table 9 summarizes the supplies re lated to the pixel array signals, where table 8 summarizes the su pplies related with all other modules time table 7. advantages and disadvantages of non-destruc- tive readout. advantages disadvantages low noise - as it is true cds. system memory required to record the reset level and the intermediate samples. high sensitivity - as the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range - as the results includes signal for short and long integrations times. requires system level digital calculations. table 8. power supplies name dc current max.current typ. max. description vaa 7 ma 50 ma 2.5v power supply column readout module. va3 10 ma 50 ma 3.3v 3.3v power supply column readout module. should be tuneable to 3.3v max. vdd 1 ma 200 ma 2.5v power supply digital modules voo 20 ma 20 ma 2.5v power supply output stages vdda 1 ma 200 ma 2.5v analog supply of adc circuitry vddd 1 ma 200 ma 2.5v digital supply of adc circuitry [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 13 of 38 the maximum currents mentioned in table 8 and table 9 are peak currents which occur once per frame (except for vres_ds in multiple slope mode). all power supplies should be able to deliver these currents except for vmem_l and vpre_l, which must be able to sink this current. the maximum peak current for vpix should not be higher than 500 ma. it is important to notice that no power supply filtering on chip is implemented and that noise on these power supplies can contribute immediately to the noise on the signal. especially the voltage supplies vpix and vaa are important to be well noise free. start-up sequence the lupa-4000 will go in latch up (draw high current) as soon as all power supplies are turned on at the same time. the sensor will come out of latch-up and start working normally as soon as it is being clocked. a power supply with a 400 ma limit is recommended to avoid damage to the sensor. it is recommended to avoid the time that the device is in the latch-up state, so clocking of the sensor should start as soon as possible (i.e. as soon as the system is turned on). in order to completely avoid latch-up of the image sensor, the next sequence should be taken into account: ?apply vdd ? apply clocks and digital pulses to the sensor to count 2048 clocks and 2048 clock_ y pulses to empty the shift registers ? apply other supplies biasing and analog signals the analog output levels that may be expected are between 0.3v for a white, saturated, pixel and 1.3v for a black pixel. 2 output stages are foreseen, each consisting of 2 output amplifiers, resulting in 4 outputs. 1 output amplifier is used for the analog signal resulting from the pixels. the second amplifier is used for a dc reference signal. the dc-level from the buffer is defined by a dac, which is controlled by a 7-bit word downloaded in the spi. additionally, an extra bit in the spi defines if 1 output or th e 2 output stages are used. table 10 summarizes the biasing signals required to drive this image sensor. for optimisation reasons of the biasing of the column amplifiers with respect to power dissipation, we need several biasing resistors. this optimisation results in an increase of signal swing and dynamic range. table 9. overview of the power supp lies related to the pixel signals name dc current max. current min. typ. max. description vres 1 ma 200 ma 2.5v 3.5v 3.8v power supply reset drivers. vres_ds 1 ma 200 ma 2.0v 2.5v 3.3v power supply dual slope reset drivers. vmem_h 1 ma 200 ma 2.5v 3.3v 3.5v power s upply memory elements in pixel for high voltage level vmem_l 1 ma 200 ma 2.0v 2.5 v 3.0v power supply memory elements in pixel for low voltage level. should be tuneable vdd 1 ma 200 ma 2.0v 2.5v 3.0v power supply for sample vpix 12 ma 500 ma 2.0v 2.5v 3.3v power supply pixel array. should be tuneable to 3.3v vpre_l 1 ma 200 ma ?400 mv 0v 0v power supply for precharge in off-stat. may be connected to ground. table 10. overview of bias signals signal comment related module dc-level out_load connect with 60 k ? to voo and capacitor of 100 nf to gnd output stage 0.7 v dec_x_load connect with 2 m ? to vdd and capacitor of 100 nf to gnd x-addressing 0.4 v muxbus_load connect with 25 k ? to vaa and capacitor of 100 nf to gnd multiplex bus 0.8 v nsf_load connect with 5 k ? to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load_fast connect with 10 k ? to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load connect with 1 m ? to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v pre_load connect with 3 k ? to vaa and capacitor of 100 nf to gnd column amplifiers 1.4 v col_load connect with 1 m ? to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v dec_y_load connect with 2 m ? to vdd and capacitor of 100 nf to gnd y-addressing 0.4 v psf_load connect with 1 m ? to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 14 of 38 each biasing signal determines the operation of a corre- sponding module in the sense that it controls speed and dissi- pation. some modules have 2 biasing resistors: one to achieve the high speed and another to minimize power dissipation. pixel array signals the pixel array of the image sensor requires digital control signals and several different power supplies. this paragraph explains the relation between the control signals and the applied supplies and the internal generated pixel array signals. from figure 9 one can see that the internal generated pixel array signals are reset, sample, precharge, vmem and row_select. these are internal generated signals derived by on chip drivers from external applied signals. row_select is generated by the y addressing and will not be discussed in this paragraph. the function of each of the signals is: reset: resets the pixel and initia tes the integration time. if reset is high than the photodiode is forced to a certain voltage, depending on vpix, which is the pixel supply; and depending on the high level of reset signal. the higher these signals or supplies are, the higher the voltage-swing. the limitation on the high level of reset and vpix is 3.3v. nevertheless, it has no sense increasing vpix without increasing the reset level. the opposite does make sense. additionally, it is this reset pulse that also controls the dual or multiple slope feature inside the pixel. by giving a reset pulse during integration, but not at full reset level, the photodiode is reset to a new value, only if his value is sufficient decreased due to light illumination. the low level of reset is 0v, but the high level is 2.5v or higher (3.3v) for the normal reset and a lower (<2.5v) level for the multiple slope reset. precharge: precharge serves as a load for the first source follower in the pixel and is activated to overwrite the current information on the storage node by the new information on the photodiode. precharge is cont rolled by an external digital signal between 0 and 2.5v. sample: samples the photodiode information onto the memory element. this signal is also a standard digital level between 0 and 2.5v. vmem: this signal increases the information on the memory element with a certain offset. this way one can increase the output voltage variation. vmem changes between vmem_l (2.5v) and vmem_h (3.3v). figure 10. internal timing of the pixel. levels are defined by the pixel array voltage suppli es (for the correct polarities of the signals refer to table 11 ) the signals in figure 10 are generated from the on chip drivers. these on chip drivers need 2 types of signals to generate the exact type of signa l. it needs digital control signals between 0 and 3.3v (int ernally converted to 2.5v) with normal driving capability and power supplies. the control signals are required to indicate the moment they need to occur and the power supplies indicate the level. vmem is made of a control signal mem_hl and 2 supplies vmem_h and vmem_l. if the signal mem_hl is the logic "0" than the internal signal vmem is low, if mem_hl is logic "1" the internal signal vmem is high. reset is made by means of 2 control signals: reset and reset_ds and 2 supplies: vres and vres_ds. depending on the signal that becomes active, the corresponding supply level is applied to the pixel. table 11 summarizes the relation between the internal and external pixel array signals. precharge_bias connect with 1k ? to vdd and capacitor of at least 200 nf to gnd. pixel drivers 1.4v table 10. overview of bias signals (continued) signal comment related module dc-level [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 15 of 38 in case the dual slope operation is desired, one needs to give a second reset pulse to a lower reset level during integration. this can be done by the control signal reset_ds and by the power supply vres_ds that defines the level to which the pixel has to be reset. note that reset is dominant over reset_ds, which means that the high voltage level will be applied for reset, if both pulses occur at the same time. note that multiple slopes are possible having multiple reset_ds pulses with a lower vres_ds level for each pulse given within the same integration time the rise and fall times of the internal generated signals are not very fast (200 nsec). in fact they are made rather slow to limit the maximum current through the power supply lines (vmem_h, vmem_l, vres, vres_ds, vdd). current limitation of those power supplies is not required. nevertheless, it is advisable to limit the currents not higher than 400 ma. the power supply vmem_l must be able to sink this current because it must be able to discharge the internal capacitance from the level vmem_h to the level vmem_l. the external control signals should be capable of driving input capacitance of about 10 pf. digital signals the digital signals control the readout of the image sensor. these signals are: ? sync_y (ah): starts the readout of the frame. this pulse synchronises the y-address regist er: active high. this signal is at the same time the end of the frame or window and determines the window width. ? clock_y (ah): clock of the y-register. on the rising edge of this clock, the next line is selected. ? sync_x (ah): starts the readout of the selected line at the address defined by the x-address register. this pulse synchronises the x-address regist er: active high. this signal is at the same time the end of the line and determines the window length. ? clock_x (ah): determines the pi xel rate. a cl ock of 33 mhz is required to achieve a pixel rate of 66mhz. ? spi_data (ah): the data for the spi ? spi_clock (ah): clock of the serial parallel interface. this clock downloads the data into the spi register. ? spi_load (ah): when the spi register is uploaded, then the data will be internally available on the rising edge of spi_load. ? sh_kol (al): control signal of the column readout. is used in sample & hold mode and in binning mode. ? norowsel (ah): control signal of the column readout. (see timing). ? pre_col (al): control signal of the column readout to reduce row blanking time. ? voltage averaging (ah): signal required obtaining voltage averaging of 2 pixels. test signals the test structures implemen ted in this image sensor are: ? array of pixels (6*12) whic h outputs are tied together: used for spectral response measurement. ? temperature diode (2): apply a forward current of 10-100 a and measure the voltage v t of the diode. v t varies linear with the temperature (v t decreases with approximately 1,6 mv/c). ? end of scan pulses (do not use to trigger other signals): ? eos_x: end of scan signal: is an output signal, indicating when the end of the line is reached. is not generated when doing windowing. ? eos_y: end of scan signal: is an output signal, indicating when the end of the frame is reached. is not generated when doing windowing. ? eos_spi: output signal of the spi to check if the data is transferred correctly through the spi. table 11. overview of the in- and external pixel array signals internal signal vlow vhigh external cont rol signal low dc-level high dc-level precharge 0 0.45v precharge (al) vpre_l controlled by bias-resistor sample 0 2.5v sample (al) gnd vdd reset 0 2.5 - 3.3v reset (ah) & reset_ds (ah) gnd vres & vres_ds vmem 2.0- 2.5v 2.5-3.3v mem_hl (al) vmem_l vmem_h notes 5. ah: active high 6. al: active low [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 16 of 38 timing and read out of the image sensor the timing of the lupa-4000 sensor consists of 2 parts. the first part is related with the cont rol of the pixels, the integration time and the signal level. the second part is related with the readout of the image sensor. as this image sensor is able for full synchronous shutter, integration time and readout can be in parallel or sequential. in the parallel mode the integr ation time of the frame i is ongoing during readout of frame i-1. figure 11 shows this parallel timing structure figure 11. integration and read out in parallel the control of the readout of th e frame and of the integration time are independent of each other with the only exception that the end of the integration time from frame i+1 is the beginning of the readout of frame i+1. the lupa-4000 sensor also can be used in sequential mode (triggered snapshot mode) wh ere readout and integration will be sequentially. figure 12 shows this sequential timing sequence. figure 12. integration and readout sequentially timing of the pixel array the first part of the timing is related with the timing of the pixel array. this implies the control of the integration time, the synchronous shutter operation and the sampling of the pixel information onto the memory element inside each pixel. the signals needed for this control are described in the previous paragraph 3.9 and in figure 10 . figure shows the external applied signals required to control the pixel array. at the end of the integration time from frame i+1, the signals mem_hl, precharge and sample have to be given. the reset signal controls the integration time, which is defined as the time between the falling edge of reset and the rising edge of sample. i ntegration i + 2 r ead frame i + 1 i ntegration i + 1 r ead frame i i ntegration i + 1 r ead frame i + 1 i ntegration i r ead frame i [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 17 of 38 figure 13. timing of the pixel array: the integration time is determined by the falling edge of the reset pulse. the longer the pulse is high, the shorter the integration time. at the end of the integration time, the information has to be stored onto the memory element for readout. timing specifications for each signal are: ? falling edge of precharge is equal or later than falling edge of vmem. ? sample is overlapping with precharge. ? rising edge of vmem is more than 200 nsec after rising edge of sample. ? rising edge of reset is equal or later than rising edge of vmem the timing of the pixel array is straightforward. before the frame is read, the information on the photodiode needs to be stored onto the memory element inside the pixels. this is done by means of the signals mem_hl, precharge and sample. when precharge is activated it serves as a load for the first source follower in the pixel. sample stores the photodiode information onto the memory element. mem_hl pumps up this value to reduce the loss of signal in the pixel and this signal must be the envelop of precharge and sample. after mem_hl is high again, the readout of the pixel array can start. the frame blanking time or frame ov erhead time is thus the time that mem_hl is low, which is about 5 sec. once the readout starts, the photodiodes can all be initialised by reset for the next integration time. the mini mal integration time is the minimal time between the falling edge of reset and the rising edge of sample. keeping the slow fall times of the corre- sponding internal generated signals in mind, the minimal integration time is about 2 sec. table 12. timing specifications symbol name value a mem_hl 5 - 8,2 sec b precharge 3 - 6 sec c sample 5 - 8 sec d precharge-sample > 2 sec e integration time > 1 sec [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 18 of 38 an additional reset pulse of minimum 2 sec can be given during integration by asserting reset_ds to implement the double slope integration mode. read out of the image sensor as soon as the information of the pixels is stored in to the memory element of each pixel, this information can be readout sequentially. as seen in the previous section, integration and readout can also be done in parallel. the readout timing is straightforward and is basically controlled by means of sync and clock pulses. figure 14 shows the top level concept of this timing. the readout of a frame consists of the frame overhead time, the selection of the lines sequentiall y and the readout of the pixels of the selected line figure 14. readout of the image sensor. f.o.t: frame overhead time. r.o.t: row overhead ti me. l: selection of line, c: selection of column the readout of an image consis ts of the fot (frame overhead time) and the sequential selection of all pixels. the fot is the overhead time between 2 frames to transfer the information on the photodiode to the memory elements. from figure 13 it should be clear that this time is the time that mem_hl is low (typically 5 s). after the fot the information is stored into the memory elements and a sequential selection of rows and columns makes sure the frame is read. x- and y- addressing to readout a frame the lines are selected sequentially. figure 15 gives the timing to select the lines sequentially. this is done by means of a clock_y and a sync_y signal. the sync_y signals synchronises the y-addressing and initialises the y-address selectio n registers. the start address is the address downloaded in the spi multiplied by 2. on the rising edge of clock_y the next line is selected. the sync_y signal is dominant and from the moment it occurs the y-address registers are initialised. if a sync_y pulse is given before the end of the frame is reached, only a part of the frame will be read. to obtain a correct initialisation sync_y must contain at least 1 rising edge of clock_y when it is active. r eadout pixels r .o.t r eadout lines l 2048 l 3 l 2 f .o.t i ntegration i + 2 r ead frame i l 1 c1 c2 c2048 [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 19 of 38 figure 15. x- and y-addressing as soon as a new line is selected, it has to be read out by the output amplifiers. before the pi xels of the selected line can be multiplexed onto the output amplifiers, one has to wait a certain time, indicated as the rot or row overhead time shown in figure 15 . this is the time to get the data stable from the pixels to the output bus befo re the output stages. this rot is in fact lost time and rather critical in a high-speed sensor. different timings to reduce this rot are explained in next paragraph. during the selection of 1 line, 2048 pixels are selected. these 2048 pixels have to be readout by 1 (or 2) output amplifier. please note that the pixel rate is the double frequency of the clock_x frequency. to obtain a pixel rate of 66 mhz, one needs to apply a pixel clock clock_x of 33mhz. when only 1 analog output is used 2 pixels are output every clock_x period. when clock_x is high, the first pixel is selected, when clock_x is low, the next pixel is selected. consequently, during 1 complete period of clock_x 2 pixels are readout by the output amplifier. if 2 analog outputs are used each clock-x period 1 pixel is presented at each output. table 13. read-out timing specifications symbol name value a sync_y >20 ns b sync_y-clock_y >0 ns c clock_y-sync_y >0 ns d norowsel >50 ns e pre_col >50 ns f sh_col 200 ns (more info rmation on this timing can be found in section 4.2.2.a) g voltage averaging >20 ns h sync_x-clock_x >0 ns [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 20 of 38 figure 16. x-addressing. from bottom to top: clock_x, sync_x, in ternal selection pixel 1&2, internal selection pixel 3&4, internal selection pixel 5 & 6 the first pixel that is selected is the x-address downloaded in the spi. the starting address is the number downloaded into the spi, multiplied with 2. windowing is achieved by a starting address downloaded in the spi and the size of the window. in the x-direction, the size is determined by the moment a new clock_y is given. in the y-direction, the syn c_y pulse determines the size. conse- quently, the best way to obtain a certain window is by using an internal counter in the controller. figure 16 is the simulation result af ter extraction of the layout module from a different sensor to show the principle. in this figure the pixel clock has a frequency of 50 mhz, which would result in a pixel rate of 100 msamples/sec. figure shows the relation between the applied clock_x and the output signal. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 21 of 38 figure 17. output signal related to clock_x signal. from bo ttom to top: clock_x, sync_x and output. the output level before the first pixel is the level of the last pixel of previous line as soon as sync_x is high and 1 rising edge of clock_x occurs, the pixels are brought to the analog outputs. this is again the simulation result of a comparable sensor to show the principle. please note there is a time difference between the clock edge and the moment the data is seen at the output. as this time difference is very difficult to predict in advance, it is advisable to have the adc sampling clock flexible to set an optimal add sampling point. the time differences can easily vary between 5 - 15 nsec and have to be tested on the real devices. reduced row overhead time timing the row overhead time is the time between the selection of lines that one has to wait to get the data stable at the column amplifiers. this row overhead time is a loss in time, which should be reduced as much as possible. output 1 sync_x clock_x: 25mhz p ixel 1 pixel2.: pixel period : 20nsec dark s aturated [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 22 of 38 standard timing (200 ns) figure 18. standard timing for the r.o.t. only pre_col and norowsel control signals are required in this case the control signals norowsel and pre_col are made active for about 20 nsec from the moment the next line is selected. the time these pulses have to be active is related with the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel and pre_col may be. after these pulses are given, one has to wait for at least 180 nsec before the first pixels can be sampled. for this mode sh_col must be made active (low) all the time. back-up timing (rot =100-200 ns) a straightforward way of reducing the r.o.t is by using a sample and hold function. by means of sh_col the analog data is tracked during the first 100 nsec during the selection of a new set of lines. after 100 nsec, the analog data is stored . the rot is in this case reduced to 100 nsec, but as the internal data was not stable yet dynamic range is lost because not the complete analog levels are reached yet after 100 ns. figure 18 shows this principle. sh_col is now a pulse of 100 ns-200 ns starting at the same moment as pre_col and norowsel. the duration of sh_col is equal to the rot. the shorter this time the shorter the rot will be however this lowers also the dynamic range. in case "voltage averaging" is required, the sensor must work in this mode with sh_col signal and a "voltage averaging" signal must be generated after sh_col drops and before the readout starts (see figure 15 ) figure 19. reduced standard rot by means of sh_col signal. pre_col (short pulse), norowsel (short pulse) and sh_col (large pulse) precharging of the buses this timing mode is exactly the same as the mode without sample and hold, except that the prebus1 and prebus2 signals are activated. it should be noti ced that the precharging of the buses can be combined with all of the timing modes discussed above. the idea is to have a short pulse of about 5 ns to precharge the output buses to a well-known level. this mode makes the ghosting of bad columns impossible. in this mode, nsf_load must be made much larger (at least 1 mohms). [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 23 of 38 figure 20. x- and y-addressing with precharging of the buses table 14. read-out timing specifications with precharching of the buses symbol name value a sync_y >20 ns b sync_y-clock_y >0 ns c clock_y-sync_y >0 ns d norowsel >50 ns e pre_col >50 ns f sh_col 200 ns (or cst low, depending on timing mode) g voltage averaging >20 ns h sync_x-clock_x >0 ns i prebus pulse as short as possible [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 24 of 38 serial-parallel-interface (spi) the spi is required to upload the different modes. table 15 shows the parameters and there bit position when all zeros are loaded into the spi, the sensor will start at pixel 0,0. the scanning will be from left to right and from top to bottom. there will be no sub-sampling or voltage averaging and only one output is used. the dac will have the lowest level at its output. when using sub sampling, only even x-addresses may be applied. figure 21. spi block diagram and timing table 15. spi parameters parameter bit nr. remarks y-direction 0 1: from bottom to top y-address 1-10 bit 1 is lsb x-voltage averaging enable 11 1: enabled x-subsampling 12 1: subsampling x-direction 13 0: from left to right x-address 14-23 bit 14 is lsb nr output amplifiers 24 0: 1 output dac 25-31 bit 25 is lsb d q c d q c spi_in to sensor clock_spi load_addr 32 outputs to sensor clock_spi spi_in unity ce ll e ntire uploadable block load_addr b0 b1 b2 b31 load_addr clock_spi spi_in command applied to sensor bit 0 bit 31 [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 25 of 38 pin list table 16 is a list of all the pins and their functionalities. pad pin pin name pin type description 1 e1 sync_x input digital input. synchronises the x-address register. 2 f1 eos_x testpin indicates when the end of the line is reached. 3 d2 vdd supply power supply digital modules. 4 g2 clock_x input digital input. determines the pixel rate. 5 g1 eos_spi testpin checks if the data is transferred correctl y through the spi. 6 f2 spi_data input digital input. data for the spi. 7 h1 spi_load input digital input. loads data into the spi. 8 h2 spi_clock input digital input. clock for the spi. 9 j2 gndo ground ground output stages 10 j1 out2 output analog output 2. 11 k1 out2dc output reference output 2. 12 m2 voo supply power supply output stages 13 l1 out1dc output reference output 1. 14 m1 out1 output analog output 1. 15 n2 gndo ground ground output stages. 16 p1 vaa supply power supply analog modules. 17 p2 gnda ground ground analog modules. 18 n1 va3 supply power supply column modules. 19 p3 vpix supply power supply pixel array. 20 q1 psf_load input analog reference input. biasing for column modules. connect with r=1m ? to vaa and decouple with c=100nf to gnda. 21 q2 nsf_load input analog reference input. biasing for column modules. connect with r=5k ? to vaa and decouple with c=100nf to gnda. 22 r1 muxbus_load input analog reference input. bi asing for multiplex bus. connect with r=25k ? to vaa and decouple with c=100nf to gnda. 23 r2 uni_load_fast input analog reference input. bi asing for column modules. connect with r=10k ? to vaa and decouple with c=100nf to gnda. 24 q3 pre_load input analog reference input. biasing for column modules. connect with r=3k ? to vaa and decouple with c=100nf to gnda. 25 q4 out_load input analog reference input. biasing for output stage. connect with r=60k ? to vaa and decouple with c=100nf to gnda. 26 n3 dec_x_load input analog reference input. biasing for x-addressing. connect with r=2m ? to vdd and decouple with c=100nf to gndd. 27 q5 uni_load input analog reference input. biasing for column modules. connect with r=1m ? to vaa and decouple with c=100nf to gnda. 28 q6 col_load input analog reference input. biasing for column modules. connect with r=1m ? to vaa and decouple with c=100nf to gnda. 29 q7 dec_y_load input analog reference input. biasing for y-addressing. connect with r=2m ? to vdd and decouple with c=100nf to gndd. 30 r3 vdd supply power supply digital modules. 31 m3 gndd ground ground digital modules. 32 l2 prebus1 input digital input. control signal to reduce readout time. 33 l3 prebus2 input digital input. control signal to reduce readout time. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 26 of 38 34 q8 sh_col input digital input. control signal of the column readout. 35 r4 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 36 r5 norowsel input digital input. control signal of the column readout. 37 r6 clock_y input digital input. clock of the y-addressing. 38 r7 sync_y input digital input. synchronises the y-address register. 39 k2 eos_y_r testpin indicates when the end of frame is reached when scanning in the 'right' direction. 40 q9 temp_diode_p testpin anode of temperature diode. 41 q10 temp_diode_n testpin cat hode of temperature diode. 42 r8 vpix supply power supply pixel array. 43 r9 vmem_l supply power supply vmem drivers. 44 r10 vmem_h supply power supply vmem drivers. 45 r11 vres supply power supply reset drivers. 46 q11 vres_ds supply power supply reset drivers. 47 r12 ref_low input analog reference input. low reference voltage of adc. (see figure 7 for exact resistor value) 48 q12 linear_conv input digital input. 0= linear conversion; 1= gamma correction. 49 p15 bit_9 output digital output 1 <9> (msb). 50 q14 bit_8 output digital output 1 <8>. 51 q15 bit_7 output digital output 1 <7>. 52 r13 bit_6 output digital output 1 <6>. 53 r14 bit_5 output digital output 1 <5>. 54 r15 bit_4 output digital output 1 <4>. 55 p14 bit_3 output digital output 1 <3>. 56 q13 bit_2 output digital output 1 <2>. 57 r16 bit_1 output digital output 1 <1>. 58 q16 bit_0 output digital output 1 <0> (lsb). 59 p16 clock input adc clock input. 60 n14 gndd supply digital gnd of adc circuitry. 61 n15 vddd supply digital supply of adc circuitry (nominal 2.5v). 62 l16 gnda supply analog gnd of adc circuitry. 63 l15 vdda supply analog supply of adc circuitry (nominal 2.5v). 64 n16 bit_inv input digital input. 0=no inversion of output bits; 1 = inversion of output bits. 65 m16 cmd_ss input analog reference input. biasing of second stage of adc. connect to vdda with r=50 k ? and decouple with c=100 nf to gnda. 66 l14 analog_in input analog input of 1 st adc. 67 m15 cmd_fs input analog reference input. biasing of first stage of adc. connect to vdda with r=50 k ? and decouple with c=100 nf to gnda. 68 m14 ref_high input analog reference input. high reference voltage of adc. (see figure 7 for exact resistor value) 69 k14 vres_ds supply power supply reset drivers. 70 j14 vres supply power supply reset drivers. 71 j15 vpre_l supply power supply precharge drivers. must be able to sink current. can also be connected to ground. 72 j16 vdd supply power supply digital modules. pad pin pin name pin type description [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 27 of 38 73 k15 vmem_h supply power supply vmem drivers. 74 k16 vmem_l supply power supply vmem drivers. 75 h15 ref_low input analog reference input. low reference voltage of adc. (see figure 7 for exact resistor value) 76 h16 linear_conv input digital input. 0= linear conversion; 1= gamma correction. 77 g16 bit_9 output digital output 2 <9> (msb). 78 f16 bit_8 output digital output 2 <8>. 79 e16 bit_7 output digital output 2 <7>. 80 g15 bit_6 output digital output 2 <6>. 81 g14 bit_5 output digital output 2 <5>. 82 f14 bit_4 output digital output 2 <4>. 83 e14 bit_3 output digital output 2 <3>. 84 d16 bit_2 output digital output 2 <2>. 85 e15 bit_1 output digital output 2 <1>. 86 f15 bit_0 output digital output 2 <0> (lsb). 87 d15 clock input adc clock input. 88 c15 gndd supply digital gnd of adc circuitry. 89 d14 vddd supply digital supply of adc circuitry (nominal 2.5v). 90 b16 gnda supply analog gnd of adc circuitry. 91 b14 vdda supply analog supply of adc circuitry (nominal 2.5v). 92 c16 bit_inv input digital input. 0=no inversion of output bits; 1 = inversion of output bits. 93 a16 cmd_ss input biasing of second stage of adc. connect to vdda with r=50 k ? and decouple with c=100 nf to gnda. 94 b15 analog_in input analog input 2 nd adc. 95 a15 cmd_fs input analog reference input. biasing of first stage of adc. connect to vdda with r=50 k ? and decouple with c=100 nf to gnda. 96 a14 ref_high input analog reference input. high reference voltage of adc. (see figure 7 for exact resistor value) 97 c14 vres_ds supply power supply reset drivers. 98 b13 vres supply power supply reset drivers. 99 a13 vmem_h supply power supply vmem drivers. 100 a9 vmem_l supply power supply vmem drivers. 101 a10 vpix supply power supply pixel array. 102 a11 reset input digital input. control of reset signal in the pixel. 103 a12 reset_ds input digital input. control of double slope reset in the pixel. 104 b7 mem_hl input digital input. control of vmem signal in pixel. 105 b8 precharge input digital input. control of vprecharge signal in pixel. 106 b9 sample input digital input. control of vsample signal in pixel. 107 b10 temp_diode_n testpin cathode of temperature diode. 108 b11 temp_diode_p testpin anode of temperature diode. 109 b6 precharge_bias input analog reference input. biasing for pixel array. (see ta ble 1 0 for exact resistor and capacitor value) 110 a8 photodiode testpin output photodiode. 111 a7 gndd ground ground digital modules. 112 b12 vdd supply power supply digital modules. pad pin pin name pin type description [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 28 of 38 remarks: 1. all pins with the same na me can be connected together. 2. all digital input are active high (unless mentioned otherwise). 3. all unused inputs should be tied to a non-active level (e.g. vdd or gnd). 113 a6 eos_y_l testpin indicates when the end of frame is reached when scanning in the 'left' direction. 114 a1 sync_y input digital input. synchronises the y-address register. 115 a5 clock_y input digital input. clock of the y-addressing. 116 a2 norowsel input digital input. control signal of the column readout. 117 a3 volt. averaging input digital input. control signal of the voltage averaging in the column readout. 118 b5 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 119 a4 sh_col input digital input. control signal of the column readout. 120 b1 prebus2 input digital input. control signal to reduce readout time. 121 b2 prebus1 input digital input. control signal to reduce readout time. 122 c1 dec_y_load input analog reference input. biasing for y-addressing. 123 d1 vpix supply power supply pixel array. 124 b4 va3 supply power supply column modules. 125 b3 gnda ground ground analog modules. 126 c2 vaa supply power supply analog modules. 127e2 e2 gndd ground ground digital modules. pad pin pin name pin type description [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 29 of 38 geometry and mechanical specifications bare die figure 22. die figure of the lupa-4000 pixel 0,0 is located at 478 m from the left side of the die and 1366 m from the bottom side of the die. pixel 0,0 pixel array of 2048 x 2048 pixels 25610 m 27200 m m m [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 30 of 38 package drawing the lupa-4000 is packaged in a 127-pin pga package. figure 23. package drawing of the lupa-4000 package [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 31 of 38 figure 24. lupa-4000 package specifications with die [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 32 of 38 bonding pads the bonding pads are located as indicated below. figure 25. placing of the bonding pads on the lupa-4000 package [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 33 of 38 bonding diagram the die is bonded to the bonding pads of the package as indicated below figure 26. bonding pads diagram of the lupa-4000 package. the die will be placed in the pa ckage in a way that the center of the light sensitive area will match the center of the package. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 34 of 38 glass transmittance a d263 glass will be used as protection glass lid on top of the lupa-4000 monochrome sensors. figure 24 shows the trans- mission characteristics of the d263 glass figure 27. transmission characteristics of the d263 glass used as protective cover for the lupa-4000 sensors 0 10 20 30 40 50 60 70 80 90 10 0 400 500 600 700 800 900 wavelength [nm] transmission [%] [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 35 of 38 handling and soldering precautions special care should be given when soldering image sensors with color filter arrays (rgb color filters), onto a circuit board, since color filters are sensit ive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. the following recommendations are made to ensure that sensor perfor- mance is not compromised during end-users' assembly processes. board assembly: device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine model devices. assembly operators should always wear all designated and approved grounding equipment; grounded wrist straps at esd protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. manual soldering: when a soldering iron is used the following conditions should be observed: ? use a soldering iron with tem perature control at the tip. ? the soldering iron tip temper ature should not exceed 350c. ? the soldering period for each pin should be less than 5 seconds. precautions and cleaning: avoid spilling solder flux on the cover glass; bare glass and particularly glass with antireflection filters may be adversely affected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropyl alcohol (ipa) is used as a solvent for cleaning the image sensor glass lid. when using other solvents, it should be confirmed beforehand whether the solvent will dissolve the package and/or the glass lid or not. ordering information disclaimer the lupa-4000 is only to be used for non-military applications. a strict exclusivit y agreement prevents us to sell the lupa-4000 to customers who intend to use it for military applications. fillfactory image sensors are only warranted to meet the specifications as described in the production data sheet. specifications are subjec t to change without notice. please contact info@fillfactory.com for more information. fillfactory part number cypress semiconductor part number lupa-4000-m cyil1sm4000aa-gbc [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 36 of 38 appendix a: lupa-4000 evaluation system for evaluating purposes an lupa-4000 evaluation kit is available. the lupa-4000 evaluation kit co nsists of a multifunctional digital board (memory, sequencer and ieee 1394 fire wire interface) and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all acquired images and movies ca n be stored in different file formats (8 or 16-bit). all setting can be adjusted on the fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state figure 28. content of the lupa-4000 evaluation kit please contact fillfactory (inf o@fillfactory.com) if you want any more information on the evaluation kit. [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 37 of 38 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. appendix b: frequently asked questions q: how does the dual (multiple) slo pe extended dynamic range mode works? a: figure 29. dual slope diagram the green lines are the analog signal on the photodiode, which de crease as a result of exposure. the slope is determined by the amount of light at each pixel (the more lig ht the steeper the slope). when the pixels reach the saturation level the analog sig nal will not change despite further exposure. as you can see without any double slope pulse pixels p3 and p4 will reach saturation before the sample moment of the analog values, no signal will be acquired without double slope. when double slope is enabled a second reset pulse will be given (blue line) at a certain time before the end of the integration time. this double slope rese t pulse resets the analog signal of the pixels below this level to the reset level. after the reset the analog signal starts to decreas e with the same slope as before the double slope reset pulse. if the d ouble slope reset pulse is placed at the end of the integration time (90% for instance) the analog signal that would have reach t he saturation levels aren't saturated anymore (this increases the optical dynamic range) at read out. it's important to notice that pixel signals abov e the double slope reset level will not be influenced by this double slope reset pulse (p1 and p2). all products and company names mentioned in this docum ent may be the trademarks of their respective holders. p4 p3 p2 p1 reset level 1 reset level 2 saturation level total integration time reset pulse double slope reset pulse read out d ouble slope reset time (usuall y 5- 10% of the total integrati on time) [+] feedback [+] feedback
lupa-4000 document number: 38-05712 rev. *b page 38 of 38 document history page document title: lupa-4000 4m pixel cmos image sensor document number: 38-05712 rev. ecn. issue date orig. of change description of change ** 310396 see ecn fpw initial cypress release *a 497132 see ecn qgs converted to frame file *b 649219 see ecn fpw ordering information update+ title update + package spec label [+] feedback [+] feedback

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